Implementation of turbo codes using verilog-HDL and estimation of its error correction capability

Turbo coding is a powerful error correction technique among forward error correcting codes. Its performance is better as it achieves near Shannon limit. This paper presents the implementation of Turbo codec for designing the Turbo encoder and decoder. The Decoder is developed based on Viterbi algorithm that incorporates hard-input and hard-output values. The errors are purposefully introduced in the encoded data to estimate error correction capability. In such case, developed Turbo decoder is able to correct two bit error in the encoded data. The Encoder and Decoder of Turbo codec are implemented using Verilog-HDL. The code is ported in FPGA for real time verification.