The synthesis technique of fault-tolerant self-timed circuits

Investigation of a fault-tolerant self-timed circuits show that a passively fault-tolerant circuit designed using traditional methods like an n-of-m reservation cannot be self-timed. This means, we need other approaches to receive circuits of this class. One possible solution was found in using of redundant gates or reservation at transistor-level. In this paper, the synthesis technique of fault-tolerant self-timed circuit is proposed. The feature of this technique is focused on the opportunity to synthesize circuit within restrictions in reliability probability, the quantity of sequentially connected transistors and circuit complexity. Logic circuits with such parameters can be used in digital devices for critical systems, energy-aware computing systems and other high-reliable application systems.