Reed-Solomon decoders for the read-write channel

Presents a hardware implementation of the Fitzpatrick algorithm (denoted by F) for solving the key equation in Reed-Solomon decoding. In addition, comparisons with the Berlekamp Massey (denoted by BM) algorithm in terms of area (FPGA resources) and speed are made. It is shown that use of the division free F algorithm results in both area and speed improvements in PRML systems.