Multiple-patterning and systematic wafer inspection of VLSI devices for yield

The design and the manufacturing of VLSI devices traditionally have been isolated affairs with different teams working on each aspect. The communication between electrical designers and process engineers has been through the form of rule files and model files. After design signoff and mask delivery the responsibility of process engineers in the fabrication line is to ensure the yield. In the absence of a design for manufacturing expertise it's a challenge for process engineers to segregate true design related patterning defects and pure process issues sometimes. It gets more complex in advanced design nodes with multiple-patterning where there are more design constraints. Wafer inspection is performed during the manufacturing to detect any non-uniformity that can affect the yield. In this paper we will explore the methodology that can increase the chances of detecting design related defects in optical and e-beam wafer inspections of patterned wafers. This approach thereby reduces the cycle time of systematic defect detection.