Performance analysis of current starved VCO in 180nm

This paper depicts a comparative study of different topologies of Current Starved Voltage Controlled Oscillator (CSVCO) of (3-stage, 5-stage and 7-stage) on the basis of power dissipation, phase noise and centre frequency parameters with the variation in number of inverter stages. This comparative analysis observe that the power dissipation can be reduced up to 28.53% for 3-stage topology w.r.t. 5-stage topology and can be reduced up-to 36.89% w.r.t. 7-stage topology of VCO. In such context a design methodology for robust and optimal current starved VCO is implemented. The circuit performance is validated using 0.18µm CMOS Technology.