Influence of quantum confinement effects and device electrostatic driven performance in ultra-scaled SixGe1−x nanowire transistors

In this work we have investigated the impact of quantum mechanical effects on the device performance of n-type in ultra-scaled SixGe_1-x nanowire transistors (NWT) for possible future applications. For the purpose of this paper Si_xGe_1-x NWTs with different Si_xGe_1-x molar fraction has been simulated. However, in all devices the cross-sectional area, dimensions and doping profiles are kept constant in order to provide fair comparison. The design of computational experiment in this work includes nanowire transistors with different gate length of 6nm, 8nm, 10nm, 12nm and 14nm. All wires are simulated with various Si_xGe_1-x ratio. As a result we have established a correlation between the mobile charge distribution in the channel and gate capacitance, drain induced barrier lowering (DIBL) and the sub-threshold slope (SS). The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also have been investigated. More importantly all calculations are based on quantum mechanical description of the mobile charge distribution in the channel. This description is based on Schrödinger equation, which is indeed preferred approach for nanowires with such ultra-scale dimensions.