RF SOI CMOS technology on 1st and 2nd generation trap-rich high resistivity SOI wafers

In this work 3 different types of UNIBOND™ Silicon-on-Insulator (SOI) wafers including one standard and two types of trap-rich high resistivity HR-SOI substrates provided by SOITEC are studied. The DC and RF performances of these wafers are compared by means of passive and active devices, coplanar waveguide (CPW) lines and partially-depleted (PD) SOI MOSFETs, respectively.