Benchmarks of a III–V TFET technology platform against the 10-nm CMOS technology node considering 28T Full-Adders

This paper presents a benchmark of a virtual III-V TFET nanowire technology platform against the predictive models of CMOS FinFETs for the 10-nm technology node. The standard 28T full adder and the 32-bits ripple carry adder are used as vehicle circuit/architecture for the comparison, respectively. Figures-of-merit including delays, energy and energy-delay plots are discussed.