Electrical characterization of Random Telegraph Noise in back-biased Ultrathin Silicon-On-Insulator MOSFETs

Random Telegraph Noise (RTN) has been studied in ultrathin SOI MOSFET by introducing a new protocol which aims to identify unequivocally the single-trap RTN signals in optimum bias conditions for its electrical characterization. The methodology combines a modified Weighted Time Lag Plot algorithm assisted with 1/f spectral scanning by gate bias. The procedure has been applied to study the influence of the back-gate bias on the RTN characteristics of the SOI devices with coupled front and back interfaces, revealing unusual characteristics compatible with the trap escaping to the gate metal contact.