Low power clock Optimized Digital De-Skew Buffer with improved duty cycle correction

In this paper, we propose an architecture for Optimized Digital De-Skew Buffer (ODDB) with improved duty cycle correction using modified edge combiner and interpolator. The transmission gate based edge combiner suffers from the problem of glitches during the setup time and overshoots and undershoots afterwards. Our NAND gate based modified edge combiner, along with the interpolator, removes the glitches, drastically reduces the overshoots and undershoots and improves the duty cycle correction to deliver stable 50% duty cycle clock. A latch based clock gating circuit is used to reduce the power consumption of the ODDB. Half Delay Line blocks are used to introduce the delay and are designed using Coarse Delay Units and Fine Delay lines. The architecture is simulated using Cadence NCSim and the clock is optimized for setup time, hold time and power consumption using the Cadence SoC Encounter. The ODDB is designed and implemented using 45 nm CMOS technology with 1.1 V power supply and is optimized for 500MHz operation. The power consumption and total cell area of the ODDB are 40.6 μW and 354.312 μm2 respectively. A 6% power saving is achieved at the cost of 14% area overhead by implementing clock gating feature in ODDB. The modified edge combiner and interpolator have also been implemented using 45nm FinFET technology (BSIM CMG) and power reduction of 19% and 45% respectively are achieved when compared to the 45nm CMOS implementation.