FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay

Fin FET circuits' performance suffers from high level of parasitics at short channel lengths despite their excellent intrinsic behavior. The effective values of a Fin FET logic gate's input and parasitic capacitances (Cin, Cp) depend strongly on its terminal voltages due to strong gate controlled modulation of carrier densities in the low doped part of the extension region which shields gate-extension fringing field capacitance. Therefore, for developing a systematic circuit design methodology with best performance, it is very important to have a quantitative understanding of Fin FET device parasitics, their dependence on circuit parameters and thereby impact on circuit delay. In this paper, we investigate the impact of this strong dependence of capacitances and its relationship with delay of a multi-stage logic circuit. For this, we study the influence of circuit parameters such as input and output transition times, inverter size (no. Of fins), load capacitance etc. On transient behavior of Fin FET inverter chains. We explain that the trend of change in inverter chain delay with respect to driver-load ratio (NF1/NF2) and load (CL) can be predicted if this phenomenon is considered.