A 3.6 mu m/sup 2/ memory cell structure for 16 Mb EPROMs

A 2.0- mu m*1.8- mu m floating-gate-type memory cell, based on a 0.6- mu m design rule, has been developed for 16-Mb EPROMs (electrically programmable ROMs). The cell size is about 40% that of the smallest 4-Mb EPROM cell reported so far. The cell also features a fast programming time of 10 mu s. The process technologies used are trench-self-aligned isolation refilled with BPSG, oxide-nitride-oxide interpoly dielectrics and bit-line contact with silicide pad and selective CVD (chemical vapor deposited) tungsten.<>