A new BiCMOS/CMOS gate comparison/design methodology and supply voltage scaling model

A novel BiCMOS/CMOS gate comparison methodology is proposed and demonstrated with fabrication in a BiCMOS technology. The concept of the sizing plane is presented as a general framework for BiCMOS gate design interpretation of performance comparison results, and extraction of the true technology dependent component in gate performance comparisons. An analytical model is derived to predict BiCMOS gate delay at reduced supply voltage, and it is verified by experimental data. The model is used to present gate design and device scaling guidelines for optimized operation under reduced supply.<>