Counting prognostication technique and results at 2.048 Mbit/s desynchronizer output for SDH equipment

Due to pointer adjustments, which play a primary role in phase noise accumulation, jitter and wander generation at the output of desynchronizer systems represents one of the most important topics in SDH (synchronous digital hierarchy) equipment. This paper describes a novel desynchronization technique-counting prognostication, to reduce the clock jitter of 2.048 Mbit/s signal in the SDH network. This technique is completely implemented by digital circuits and is apt to integrated. Moreover, analyses of jitter performance and experiment results are given to show that the recovered clock has very small jitter (about 0.04 UI) and has little jitter accumulation.