Fairness and performance limits of contention resolution mechanisms for input buffered switches

Input buffering is becoming the buffering method of choice not only for ATM switching but also for gigabit routers and high-throughput Ethernet switches. Pure shared memory and output buffered switching architectures are either not able to provide the necessary amount of buffering space to support bursty traffic or they suffer from packet losses at asymmetric load patterns due to limited speed-up capabilities. Input buffers on the other hand have only to operate at the speed of the input lines and can be implemented up to arbitrary buffer sizes by using off-the-shelf DRAMs. Different input buffered switches can mainly be distinguished by the way contention resolution is handled. This paper investigates the principal performance capabilities and limits of input buffered switching architectures in comparison to the well known performance of output buffering that always constitutes the theoretical limit. The analysis starts from known equations for the queueing behaviour of input buffering with FIFO queues. It is shown that the usage of per-output sub-buffering is in principle able to provide the same mean buffer lengths as pure output buffered switches.