An Optimization Method for Embarrassingly Parallel under MIC Architecture

Nowadays, heterogeneous architecture of CPU plus accelerator has become a mainstream in supercomputing. Intel lauched its Xeon Phi coprocessor in this context. It uses Intel's many-core architecture, which greatly improves the single node parallelism. This paper studies the optimization of embarrassingly parallel programs under Intel MIC architecture, to maximize the utilization of CPU and Phi processor, and reduce the running time of parallel programs, by combining the computing power of CPU and Phi. This so-called embarrassingly parallel program often have do all main loops, that is, there are no dependencies between iterations, so they can be fully parallelized. This do all loop exists in many typical parallel programs. We come up with a loop allocation method for do all loops under this CPU/MIC architecture, to satisfy the above performance objectives.