Space and Execution Efficient Formats for Modern Processor Architectures

Sparse matrix-vector multiplication (shortly spMV) and transposed spMV (shortly spMTV) are the most common routines in the numerical linear algebra. Sparse storage formats describe a way how sparse matrices are stored in a computer memory. Since the commonly used storage formats (like COO or CSR) are not sufficient for high-performance computations, extensive research has been conducted about maximal computational efficiency of these routines. For modern CPU architectures, the main bottleneck of these routines is the limited memory bandwidth. In this paper, we introduce a new approach for these routines for modern processor architectures using a space efficient hierarchical format, which can significantly reduce the amount of transferred data from memory for almost all types of matrices arising from various application disciplines. This format represents a trade-off between space and execution efficiency. The performance of these routines with this format seems to be very close to the hardware limits.