Research on Topology and Policy for Low Power Consumption of Network-on-Chip with Multicore Processors

On-chip multi-processor technology has developed rapidly with progress in manufacturing processes, resulting in a continuous increase in the number of processor cores on a chip. However, increase in the number of cores leads to difficulties in communication between cores. To overcome this disadvantage, a network-on-chip (NoC) was proposed, which replaced traditional bus connections between cores using routers, resulting in more fluent communication. Although the quality of communication services has improved, the NoC still faces several technical challenges, such as ensuring the execution time, controlling the network delay effectively and reducing power consumption reasonably. In this study, we introduce a new topology and policy in router of NoC.in topology, we let more components connected with on router, and this has been beneficial in reducing power consumption because of the reduction in the number of routers. In policy, we adjusting the communication scheduling of routers and dynamically checking changes in port sequences has improved the communication infrastructure and increased the network throughput. Besides, dynamically adjusting the position where the minimum unit of data is stored in the router significantly reduces the congestion of the network and relieves the pressure of link. Compared with present techniques, through the power consumption is reduced by about 15% -- 20%. And can get more effect when compared with flattened butterfly this effect will be more pronounced with the increase in the cores and tasks.