A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMs

A novel three-dimensional memory cell called the surrounding gate transistor (SGT) cell has been developed for 64/256-Mb DRAMs (dynamic RAMs). In the SGT cell structure, a transfer gate and a capacitor electrode surround a pillar silicon island. Contact of the bit line is made on top of the silicon pillar. All devices for a memory cell are located in one silicon pillar. Each silicon pillar is isolated by matrixlike trenches. Therefore, there is no intercell leakage current even in small cell-to-cell spacing. The SGT cell can achieve an extremely small cell size of 1.2 mu m/sup 2/ and a large capacitance of 30 fF using a relaxed design rule of 0.5 mu m. The cell has been fabricated and its functionality confirmed.<
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