Wafer-level shellac-based interconnection process for ultrathin silicon chips of arbitrary shape

This work addresses the interfacing of ultrathin microchips based on silicon (Si) with highly flexible, polymer-based cables of several centimeters in length. More specifically, we target chronically implantable neural probes with cross-sections as small as 120×50 μm2 designed for intra-cortical applications. The study describes the development of a novel fabrication process based on the temporary fixation of multiple Si chips in a sacrificial polymer matrix. In contrast to existing approaches, our post-CMOS compatible process provides in particular economic advantages since chips are temporarily transferred from standard Si substrates into shellac for the purpose of chip interfacing, thereby saving valuable area on the Si substrate. Furthermore, the shellac matrix inherently adaptes to any chip shape during device embedding. This avoids preparing expensive Si handle wafers with design-dependent recesses realized using micromachining. We combined multiple 50-μm-thick Si chips with 10-μm-thin Parylene-C interconnects and successfully released the assemblies from the sacrificial shellac substrates. We verified the electrical connection between cable and chip at contact dimensions as small as 10×10 μm2 and tested the chip/cable bond in a 90°-peel test with excellent results.