An efficient implementation method of H.264 CAVLC video coding using FPGA

CAVLC is an efficient entropy coding technique used in modern video coding standards such as H.264 and H.265 (V9). It is used for reducing and removing the redundancy of the transformed quantized coefficients. The previous CAVLC implementations code the Luma blocks then Chroma blocks this leads to low throughput of encoded blocks. In this paper, an efficient implementation of CAVLC is proposed. The Luma and Chroma blocks are processed simultaneously. It deals with Chroma components and Luma components then generate the output codes respectively. Our proposed parallel algorithm of CAVLC will increase the throughput of encoding blocks at high bit rates. This leads to reduce the time of generation of the bit stream by about 40%. The proposed architecture synthesized with 100MHz clock using Nexys-4 kit based on the latest Artix-7 FPGA XC7A100T-CSG34 from Xilinix.