Compact Doherty Power Amplifier Design for 2 $\times$ 2 Multiple-Input Multiple-Output System

A triple-transistor Doherty power amplifier (PA) architecture that supports two identical input and output signals is investigated. Two peaking PAs and a single carrier PA are arranged to operate at high and low power regions. This structure can be used in 2 × 2 multiple-input multiple-output transceiver. Compared with classic configuration that needs four transistors to realize the same functionality, the proposed design greatly reduces the overall circuit size and cost. Theoretical analysis is given for deep understanding of the operational principle regarding this novel Doherty PA. To validate the effectiveness, a prototype PA corresponding to the proposed architecture is implemented based on Cree's gallium nitride high electron mobility transistor transistors. Experimental results demonstrate very high drain efficiencies at both saturation and back-off regions.