Packaging induced stress effects investigations on 40nm CMOS technology node: Measurements and optimization of device shifts

This work aims at implementing sense structures dedicated to the determination of the electrical responses of device due to packaging and to find ways of minimizing the stress effects on typical devices. Calibration step is carried out thanks to a four-point bending machine on 4n&4p MOS rosette sensors and bandgap (BG) structure. It is combined to 3D finite element (FE) simulations with the Ansys software on two typical packages (a large and a small die). The results show significant mobility changes in distinct regions of the dies: up to -11% diminution was found on nMOS, while pMOS are boosted up to +4%. A dedicated simulation strategy is also proposed to make the bridge between the bandgap coefficients previously calibrated and the stress components. Package simulation results show variations of the output voltage around -0.35% at the central region of the large die and -0.24% for the small one. In addition, the larger the die is, the higher the variations are. In order to reduce the impact of packaging on the device shifts, parametric studies were performed on a standard package, consisting in the variation of several component features. This allowed obtaining the device shifts close to zero: nMOS→0.008%, pMOS→0.0012% and BG→10^-5% over a large area in the middle of the die. These studies demonstrated that the effects of packaging steps at the transistor and circuit scales cannot be neglected anymore and that managing the components parameters can minimize these effects.