Flux challenges in flip-chip die-attach

A new trend is now well-established in the semiconductor assembly industry - copper-pillars topped with solder microbumps are replacing the standard flip-chip solder bumps. Driving this trend is the demand for increased functionality in smaller and thinner devices. This creates an interesting challenge for assemblers as they are faced with finer pitch and reduced clearance (height of the die-to-substrate) in their assembly processes. The most common solder-based packaging interconnect method is the attachment of the flip-chip to the carrier (either a substrate or a leadframe) using solder that is assisted by flux as a medium for removing oxides. Historically, a water-soluble flux has been used for flip-chip attachment, but the drive towards finer pitch components combined with the reduced copper-pillar height makes aqueous cleaning of flipchip flux residues more challenging. An emergent failure mode is damage to the thinned chip itself, and the subsequent yield loss during aqueous jet impingement and drying processes. The shift towards using semiconductor-grade ultra-low residue no-clean fluxes, which eliminates the cleaning processes, is therefore inevitable, and allows flip-chip applications to meet industry roadmap challenges for 14nm and future nodes. The use of ultralow residue flux also optimizes underfill adhesion and decreases possible outgassing during underfill curing. This paper discusses the variety of new and emerging challenges in the flip-chip attachment process, including the use of different types of flipchip flux. Concerns involving the application of the flux, the reflow process, the cleaning process, and compatibility with the underfill will be discussed in detail.