Power amplifier based on 50 Ω Load impedance using boost DC-DC converter for APT

This paper presents a power amplifier (PA) based on a boosted supply voltage using a boost DC-DC converter to eliminate the load impedance matching network for handset applications. With appropriate transistor size and boosted collector/drain voltage, the optimum load impedance of the PA can be around 50 Ω to have a required output power level. As a result, loss and bandwidth limitation from the output matching network can be greatly mitigated. In addition, efficiency improvement at low output power level can be obtained by decreasing the output voltage of the boost DC-DC converter, which is an average power tracking (APT) operation. To prove the proposed concept, the PA with a boost DC-DC converter was implemented for the 1.88 GHz band. Using a 16-QAM uplink LTE signal with a peak-to-average power ratio (PAPR) of 7.2 dB and a channel bandwidth of 5 MHz, the PA with a drain supply voltage of 12 V exhibited an output power of 27.8 dBm, a power-added efficiency (PAE) of 41.3%, and power gain of 12.5 dB for the given adjacent-channel leakage power ratio (ACLR) of −30 dBc. For a supply voltage of 4 V from the DC-DC converter, a high PAE of 33.8% is maintained for a back-off output power of 18.3 dBm.