Effect of finger spacing on the gain of a silicon avalanche photodetector compatible with CMOS technology

We present a theoretical study of the gain of a CMOS compatible thin submicron Si-CMOS p-i-n avalanche photodetector (APD) suitable for high-speed, low-voltage operation. A 2-D model is used to estimate the avalanche build-up of carriers in the depleted region considering the dead-space effect. The model is also considered the effects of diffusion of carriers from the substrate region. The results on the gain are shown as a function of finger spacing and bias.