Buffering strategies for ultra high-throughput stream processing

The insatiable demand for more data content and higher video resolution over the Internet requires a corresponding increase in communication data rates. Handling the massive acquisition, aggregation, and propagation of these communication signals requires high-throughput data processing. ASICs and FPGAs are the only devices capable of processing the data in real time at the highest throughput requirements. Traditionally, when data throughput exceeds the clock rate of these devices, data are sourced in parallel streams. However, current highlevel synthesis tools fail to efficiently handle data distributed across parallel streams while trying to meet low latency and real time requirements. This paper presents an algorithm to automate efficient allocation of data across parallel streams and computations with varying memory access requirements. The proposed approach exceeds the performance of current high-level tools by 57% in latency and 55% memory usage for two samples per clock, with more impressive reductions of 88% in latency and 83% in memory usage at eight samples per clock.