Subthreshold bandgap voltage reference aiming for energy harvesting: 100na, 5 ppm/c, 40 ppm/v, psrr -88db

The proposed analog design belongs to a class of CMOS resistor free bandgap voltage (VBG) references whose proportional to absolute temperature (PTAT) voltage (VPTAT) is generated by summing K number of thermal voltages (VT) via a string of K number of self-cascodes (SC). The VBG is produced by adding this VPTAT to a complementary to absolute temperature (CTAT) voltage (VCTAT), which is generated by base-emitter voltage (VBE) of a parasitic vertical bipolar junction transistor (BJT) in 0.18u digital CMOS. Compared to prior art, this circuit's contributions are: (1) The design employs similarly configured SCs in both the PTAT SC string as well as in the bandgap's bias current (IBIAS) circuitry, where IBIAS feeds the SCs in the PTAT string, thereby generating a stable VPTAT over power supply and process variations; (2) AC, and transient performances are benefited because the VPTAT and VCTAT signal paths are made independent and in series with one another. Thus, the concurrent positive and negative VPTAT loops inherent in conventional bandgaps, which are more prone to oscillation, are avoided; (3) Comparatively speaking, noise performance and die yield are fundamentally improved since VPTAT is generated via summation here, instead of multiplication that is operant in conventional bandgaps. Moreover, IDD and IBIAS are primarily a function of MOSFET's mobility (u) and VT, and independent of MOSFET's threshold voltage (VTH), which improves yield to specifications over fabrication process variations. Simulations, including montecarlo (MC) and worst-case (WC), show the following specifications are achievable: VBG ~ 1.238 V at VDD ~ 1.3 V; IDD ~ 100 nA; Voltage Coefficient (VC) ~ ±20 ppm/V; Temperature Coefficient (TC) ~ ±2.5 ppm/C with 0C < T < 70C; Power Supply Rejection Ratio (PSRR) ~ -88dB; Start-up time (tsu) ~ 38 millisecond; and IDD variations ~ ±7% over process corners; die size ~ 85um/side.