Network topology exchange between NetFPGA-10G and Quagga routing platforms

Internet is getting faster and more dynamic daily, with increasing number of users, and mobility on the network. This puts a high load on Internet routers, which are the most important component of the Internet infrastructure. In this paper, we present and analyze integration of Quagga open-source routing software and NetFPGA-10G hardware platform. These two open-source platforms allow us to evaluate speed of connection between control and data planes which is crucial for flexibility of Internet routers and their potential to follow fast changes on the Internet. In particular, we measure how fast lookup tables calculated by the control plane can be downloaded to hardware in order to allow high-speed packet forwarding using balanced parallelized frugal lookup (BPFL) algorithm, which we proposed earlier. BPFL achieves high speed in packet forwarding using parallel processing on FPGA chip. Further, BPFL uses less on-chip memory compared to other lookup algorithms, and, for this reason, it can more scalable support IPv4 and IPv6 addresses.