Channel Profile Design of $\text{E}\delta $ DC MOSFET for High Intrinsic Gain and Low $V_{T}$ Mismatch

In this paper, we present a systematic procedure for the design of a channel profile of an epitaxial delta doped channel (EδDC) MOS transistor so that the intrinsic gain (A_u) is high and the threshold voltage (V_T) mismatch is low. Analytical study shows that a tradeoff relation exists between low V_T mismatch and high A_V with respect to the thickness of the channel region. Therefore, careful selection of the design parameters is essential in order to have an optimum performance. The performance characteristics of the designed device are subsequently verified through Technology Computer Aided Design simulations. In order to demonstrate the benefits of using optimized EδDC transistor, we compare its performance with that of a reference deeply depleted channel MOS transistor. The performance improvement of using optimized EδDC transistor with respect to the chosen objectives is clearly explained.