A substrate triggered lateral bipolar circuit for high voltage tolerant ESD protection applications

In this work, a substrate triggered HV tolerant lateral NPN (LNPN) design is presented for a fully salicided, 0.35 /spl mu/m, 90 /spl Aring/ gate oxide, thin-epi, retrograde n-well, bulk CMOS technology. The design is highly independent of power rail capacitance, exhibits reduced pin leakages at elevated temperatures and is fully compatible with the baseline process. The design has been shown to achieve over 2 kV of HBM performance for all positive discharge stress modes, which are the most difficult to protect against in epi processes.