An evolutionary algorithm based approach for VLSI floor-planning

As the number of transistors in a single Very Large Scale Integrated (VLSI) chip is countless, the IC design has become much more complex. Floor-planning is an essential design step for hierarchical, building-module design methodology. Floor-planning provides an early feedback that evaluates the architectural decisions; estimates the chip areas; delays and congestion caused by wiring. As the technology advances, the design complexity increases and the circuit size gets larger. To cope up with the ever increasing design complexity, hierarchical design and intellectual property (IP) modules are widely used. This trend makes floor-planning much more critical to the quality of the VLSI design than ever. This paper presents an evolutionary algorithm called Craziness Based Particle Swarm Optimization algorithm (CRPSO) for floor-planning optimization of VLSI chip. CRPSO is a modified version of Particle Swarm Optimization (PSO) Technique and is employed to speed up the local search and to improve the precision of the solution. The main objective of floor-planning optimization is to minimize the chip area and the interconnection wire length. Floor-planning directly correlates to the cost of the silicon chip. The simulation results show that the CRPSO based floor-planning outperforms those of the other approaches reported in earlier literature.