FPGA implementation of a coherent optical receiver front-end: High-level design and test methodology

This paper presents an FPGA implementation of the front-end of a single-carrier coherent optical receiver for optical networks. The receiver is based on a number of spectral-efficient techniques, such as polarization multiplexing and 16-QAM modulation formats. The FPGA implementation was tested with received traces (time series) obtained from optical simulation for scenarios that operate with channel data rates of 112 Gb/s. Primary emphasis is given to the use of powerful high-level design tools and to efficient testing methodology for FPGA implementation.