Simulation Environment Based on SystemC and VEOS for Multi-core Processors with Virtual AUTOSAR ECUs

The extension of time-triggered message-based on-chip architectures towards an AUTOSAR MPSoC platform helps to achieve the AUTOSAR goals, in particular with respect to fault isolation and temporal predictability. Simulation environments enable early analysis and performance tests of the software for MPSoC platforms. However, there is no simulation environment that combines on-chip network communication and AUTOSAR-based software. This paper presents a simulation environment for TIme-triggered MEssage-based multi-core platforms based on AUTOSAR (TIMEA). Simulated application cores serve as virtual Electronic Control Units (ECUs), each containing an AUTOSAR operating system and a Run-Time Environment (RTE). The presented simulation environment performs a co-simulation of the AUTOSAR software, the natural environment and the time-triggered NoC. An on-chip simulation model in SystemC is combined with AUTOSAR simulation tools from dSpace. The capability of the simulation environment is evaluated using an antilock braking use case.