Yield and reliability enhancement for 3D ICs

In order to improve the assembly yield in Through-Silicon Via (TSV) fabrication process, we develop a fault model considering TSV coupling effect that has not been carefully investigated before. It leads our attention to a unique phenomenon, i.e., the faulty TSVs can be clustered. Thus, we propose a novel TSV redundancy architecture, composed of a light-weight switch design and two effective and efficient repair algorithms. Experimental results show that they have much higher repair rate than the existing solutions w.t. or w.o clustered TSV faults. We extend this TSV redundancy architecture to address two critical challenges: catastrophic TSV failure with extremely clustered TSV faults; circuit timing error that occurs in the runtime induced by the latent TSV defects. These works provide a systematic way to improve the yield and reliability for 3D ICs, which is of significance impact, as a percentage increase of the yield means millions of dollars.