A few behavioral modeling options for balancing verification coverage and credibility

The purpose of verification is to reduce the risk of silicon not meeting performance specifications or worse yet, not functioning. Since the silicon does not yet exist, verification depends on simulations. Simulations in turn depend on models. In verification terms, the classical modeling tradeoff between speed and accuracy translates into a tradeoff between test coverage and model credibility (or validity). Transistor-level models produce the most credible simulations but slow run times and convergence problems severely limit test coverage. At the other extreme, a high level flat model quickly simulates all required tests but is least credible because the high level of abstraction greatly increases the chances for un-modeled circuit bugs and other relevant omitted behaviors. A “good” modeling boundary balances coverage and credibility. The balance is subjective because it depends on schedule, available resources, and acceptable risk. Given how strongly verification depends on the overall modeling strategy, it helps to have as many modeling options as possible. This tutorial describes a few modeling methods to balance coverage and credibility.