Optoelectronic integration for reduced power dissipation in optical interconnect

Increasing data interconnect densities and rates drive the requirements for optical high-speed interfaces to ASICs (e.g. network switches, routers, CPU's). In contemporary implementations, as illustrated in Figure 1a, optical transceivers (such as SFP and QSFP modules and AOCs) are located at the card edge. In such an architecture increasing data rates aggravate electrical signal integrity issues due to reflections at optical connectors and losses (dielectric and skin-effect) in the relatively long traces on the card PCBA connecting the electrical pads of the switch chip with the fingers of the transceiver module. To overcome those challenges, advanced (power hungry) electrical I/Os (re-timers, equalizers,) on the ASIC and the optical transceivers are required. Also advanced (costly) PCB materials may be needed. An approach to reduce those signal integrity problems is to reduce the distance between the optical transceivers and the ASIC by moving the transceivers from the board edge to the inside of the shelf as illustrated in Figure 1b. Here the optical signals are routed to the front panel by means of optical fibers. As an additional benefit, embedding the transceivers in the card may increase the achievable density at the card edge. However, it also adds more stringent reliability and thermal management requirements for the optical transceivers. An example is the IBM Power 775 System where transceivers are located around a HUB ASIC [1]. The most ideal solution has the ASIC and the optical transceivers integrated or co-packaged as shown in Figure.2c. This approach virtually eliminates the signal integrity challenges and enables the highest interconnect density.