Globally Asynchronous Locally Synchronous Design Methodology in ASICs for Wireless Communications

Globally Asynchronous Locally Synchronous (GALS) methodology has been researched for years as a potential solution for complex ASIC integration. Different techniques have been proposed, and some of them are nowadays considered by the industry as well. In this talk a broad overview of the GALS interfaces will be performed and their potential applications disclosed. The expected advantages and associated challenges imposed by GALS techniques will be discussed. The brief overview of the activities in IHP in the last decade will be presented with the focus on system integration of DSP ASICs for wireless communications. High performance wireless communication blocks are usually based on optimized datapath processing which could be partitioned into the independent clock domains. On the other hand due to its complexity, mobile use and need for mixed-signal integration, such systems often require additional measures for system integration, switching noise reduction and power optimization. The main focus will be on most promising features of GALS - switching noise reduction by desynchronization of the local blocks communication. The topic will be disclosed starting from the theoretical model up to the respective test chip implementation. The baseline for implementation is GALS based on pausible clocking. In addition, the other properties, such as power and area overhead, of the GALS ASICs will be evaluated. The talk will be followed with the set of practical examples - complex test ASICs. This includes 60 GHz OFDM baseband processor in 40 nm CMOS named Moonrake Chip, and 120 GHz radar chip in 130 nm BiCMOS technology, named Lighthouse. In order to implement such GALS chips specific ASIC design flow has been proposed and utilized. Finally, this talk will also try to provide the outlook to the interesting open research problems and potential future use of the GALS systems.