Best engineering practice for thermal characterization of stacked dice FPGA devices

This paper presents a couple of new methodologies regarding package characterization. An important shortcoming of the JEDEC methodology for single-die packages is that it does not account for the real-world scenario of a package's boundary condition. A new methodology is proposed to overcome this shortcoming by accounting for typical PCB conductivities and heatsink attachments to packages. The second methodology, presented in the paper, shows a better way to develop DELPHI-based boundary condition independent compact thermal models for 2.5D packages with multiple dies mounted on an interposer. This methodology, based on DELPHI-based techniques, accounts for the interaction between the multiple dies in a package. This is done by modifying the resistors generated from the optimization process. A number of verification cases show good fidelity of the compact thermal model to the detailed model.