Subthreshold capable, asynchronous FPGA in a 14nm SOI process

We have designed a subthreshold-enabled FPGA (seFPGA) that has been sent for fabrication. The seFPGA has a general purpose, but asynchronous architecture that contains 50,880 16-bit LUTs with 4 voltage domains. Furthermore, the architecture is appropriate for the floating-gate or SRAM state storage.