Efficient hardware design of N-point 1D-DCT for HEVC

This work presents three hardware designs for N-point 1D-DCT used in high efficient video coding standard, which were designed taking into account all of the standard requirements, such as multiple transform sizes, finite precision approximations of DCT core matrices, scale factors, offset values, and output bit depth. The hardware architectures are flexible and parameterizable from the viewpoint of the number of inputs (N) and the number of bits of each input (n). They were implemented using one partial butterfly unit, one N/2-point 1D-DCT, N/2 multiple- constant-multiplication units, and N/2 adder units. Also, the proposed architectures were designed using minimal bit representation for the signals, shift-add blocks instead multiplications and new structures of MCM blocks in order to minimize the hardware resources and increase the performance. Synthesis results show that the proposed designs use less area and have higher operation frequency and throughput than other designs presented in the literature. Furthermore, they can support ultra-high-definition video resolutions.