Fully CMOS compatible gate-shifted LDD-NMOS

This work investigates, through extensive two-dimensional device simulation and experiments on prototypes, the prospects of integrating high-voltage blocking capability NMOS devices into a standard submicron, low cost, CMOS technology with no extra processing steps. With this new device, GSLDD-NMOS, breakdown voltages in the range of 50 volt and specific ON-resistances in the range of 3 m/spl Omega/.cm/sup 2/ were attained. Its performance is compared with other high performant devices, fabricated in more sophisticated technologies. The proposed device is, therefore, highly suitable for the implementation of very low cost smart power circuits.