Implication of hysteretic selector device on the biasing scheme of a cross-point memory array

We analyze the effect of hysteresis in the correlated material (CM) based selector devices on the choice of the word-line and bit-line voltages of a cross-point memory array. Considering a magnetic tunnel junction as the memory device, we also evaluate the dependence of array leakage and performance on the CM characteristics. While insulator-to-metal transition (IMT) in the CM plays a pivotal role in determining the voltage biases for proper functionality, we show that metal-to-insulator transition (MIT) also has an important effect on the array power-performance. If MIT switching time is large compared to the setup time, the read/write speed may be limited by MIT, resulting in performance loss. We show that the performance can be recovered by choosing appropriate voltage biases. We define the region of operation for the voltage biases constrained by MIT to ensure no performance penalty due to metal-to-insulator transition. For the read operation, MIT constrained region of operation leads to minimal or no leakage penalty. Thus, optimal choice of bias voltages for read yields maximum performance and energy efficiency. However, for the write operation, high write voltage shrinks the region of operation, thus offering limited choices for the voltages, leading to leakage increase. The leakage penalty reduces with decreasing hysteresis of the CM. While leakage increase at iso-performance can be as large as 21X for 75mV of hysteresis, it reduces to 2.6X for hysteresis of 28mV. For hysteresis > 100 mV, the MIT constrained region of operation vanishes and the only design choice that remains is increasing the write cycle time.