Fourth-order cascade SC /spl Sigma//spl Delta/ modulators: a comparative study

Fourth-order cascade /spl Sigma//spl Delta/ modulators are very well suited for IC implementation using analog sampled-data circuits because of their robust, stable operation and their capability to achieve high resolution and wide bandwidth with moderate power consumption. However, their optimum realization requires careful consideration of their performance degradations due to the hardware nonidealities. This paper presents a comparative study of the influence of finite op-amp gain and capacitor mismatch on the performance of fourth-order cascade /spl Sigma//spl Delta/ modulators realized by means of switched-capacitor circuits. It considers single-bit and multibit quantizers and draws a number of comparative remarks validated by time-domain behavioral simulations.