Design and implementation of area efficient multi-ported memories with write conflict resolution

Multiported memories (MPMs) are essential building blocks for increasing issue width in today's superscalar processors and enabling instruction level parallelism. FPGAs are an attractive platform for realizing MPMs, as they contain dual ported embedded memory blocks of fixed number and size which can be used to construct memories with more ports. The Live Value Table (LVT) technique has been used to construct MPMs with an arbitrary number of ports. Here we describe modifications to LVT enabling us to construct MPMs which are superior with respect to area of both block RAMS (BRAMs) and logic elements (LEs). As an example, we build a 32-bit wide, 256-bit deep 4W/8R memory containing 43% fewer LEs and 75% fewer BRAMS, compared to an MPM based on the original LVT techniques. We also study the effect of write port to read port ratios on performance and we propose a hardware mechanism for write conflict detection and resolution.