Power, Energy and SNM Optimization of 6TSRAM Cell Using Power Gating Technique

SRAM is the most important part of memory designs and are indispensable in several applications that include System on Chips (SoCs). Following the Moore's law, power dissipation and stability has become a major area of concern in sub-micron SRAM cell design with continuous technology scaling. In this paper, power gating technique is proposed to reduce the leakage power and energy consumption in the circuit with increased noise margin. HSPICE simulation of the circuit is done for 32nm and 45nm Berkeley Predictive Technology Model (BPTM) at supply voltage of 0.9V and 1V respectively. A comparative analysis of basic and conventional SRAM is done in both 32nm and 45nm technology. Results show the significant increase in power and energy with improved static noise margin (SNM) as compared to non power gated conventional 6TSRAM cell.