Design and Implementation of Floating Point Divide-Add Fused Architecture

Many Floating Point operations have been acknowledged to be useful for many real time graphic and multimedia application as well as DSP processors. Many Digital Signal Processing algorithms use Floating point arithmetic, which requires millions of calculations per second to be performed. For such stringent requirements, design of fast, precise and efficient circuits is the goal. This brief presents a dedicated unit for the combined operation of floating-point (FP) division followed byaddition/subtraction -- the divide -- add fused (DAF). The goal of this unit is to increase the performance and the accuracy of applications where this combined operation is frequent, such as the interval Newton's method or the polynomial approximation. The proposed DAF unit presents a similar architecture to the FP multiply accumulateunits. The main difference is represented by the divider, which is implemented using digit-recurrence algorithms. An important design trade off regarding DAFis represented by the number of required quotient bits. We present the impact of the adopted number of quotient bits on accuracy, cost, and performance. We show that the proposed implementations have better accuracy with respect to the solution based on two distinct units: an FP divider and an FP adder. This implementation is suitable for lower latency, accuracy and best cost-performance trade off. The proposed unit is synthesized for4vfx60ff672-12 Xilinx Spartan-6 FPGA.