Efficient parallelisation of an MPEG-2 codec on a TMS320C80 video processor

This paper presents an efficient implementation of an MPEG-2 video codec on a specialised digital signal processor, the TMS320C80 MVP. The parallelisation strategies involved in our work are overviewed, the system-level task distributions are presented and the low-level optimisations are described. The obtained encoder-decoder is able to encode CIF-format 4:2:0 colour intra- and P-pictures in real-time (25 Hz) with one motion vector per 16/spl times/16 macroblock.