Analytical Design Methodology for Generic Doherty Amplifier Architectures Using Three-Port Input/Output Networks

In this paper, a new Doherty amplifier architecture along with an analytical based design methodology is proposed. The proposed architecture uses novel three-port network as the output matching/combining network (OMCN). The three-port OMCN performs the power combining for any arbitrary output power ratios from the two transistors of the Doherty amplifier. It also performs the impedance matching from any arbitrary complex load impedance to the optimum impedances for both transistors at peak output power. Commonly in Doherty amplifiers, an optimum performance at peak power and a sub-optimum performance at power back-off are often obtained. Using the proposed output network, optimum performance can be reached at power back-off, as well as at peak power. Another three-port network is proposed for input matching/dividing network (IMDN) at the input of the proposed Doherty amplifier. The three-port IMDN is designed to perform the power division with any arbitrary division ratio, adjust the arbitrary phase difference between the input signals to the two transistors, and provide the impedance matching from any arbitrary complex source impedance to the optimal source impedances for the two transistors. To verify the provided theory, two prototype amplifiers are designed and tested. A 12-W amplifier is designed for a 50-Ω source and load impedances at 1 GHz. Another 12-W amplifier is designed at 1 GHz for complex source and load impedances. Both amplifiers have efficiency of higher than 50% at 7-dB output power range.