Thermal aware FPRM based AND-XOR network synthesis of logic circuits

With the advent of incorporating increased number of complex logic blocks within a VLSI chip, power-density is increasing. Power-density directly converges into temperature which reduces the yield of the circuit. Adverse affect of power-density reduction is increase in area. So, there is a trade-off between area and power-density. Previous works has been done on the Fixed Polarity Reed-Muller (FPRM) AND-XOR realization for its reduced area or low power realization. In this paper, we present a Genetic Algorithm(GA) based non-exhaustive heuristic to increase the sharing of product terms by selecting the proper polarity of input variables in FPRM expansion and a suitable area and power-density trade-off has been enumerated. Incorporation of the power-density as a fitness constraint in FPRM based optimization for temperature analysis is the first ever effort. The proposed algorithm has been validated with the LGSynth93 benchmark circuit.